It is known as the so-called dark silicon problem that all the transistors cannot be caused to operate simultaneously because of the balance with power consumption.
Due to the abovementioned problem, there is a case where an electronic circuit needs limitation of the operation thereof as necessary. In other words, because there is a fear that simultaneous operation of all the circuits results in excessive power consumption and malfunction, there is a case where it is required to limit the operation of the circuit as necessary and thereby prevent excessive power consumption.
As one of the techniques for preventing such an operation of the circuit, Patent Document 1 is known, for example. Patent Document 1 discloses a processor which includes a power accumulation part accumulating power information about power consumed during issuance of an instruction, a comparison part comparing the accumulated power information with a given threshold, and a control part blocking another instruction from being issued. According to Patent Document 1, in a case where the accumulated power information exceeds the threshold, the control part blocks another instruction from being issued.
Patent Document 1: Japanese Unexamined Patent Application Publication No. JP-A 2013-518346
A multi-core processor configured by integrating a plurality of processor cores in one package is known. In a multi-core processor, arithmetic processing is executed in each processor core. Thus, power is consumed by each processor core depending on arithmetic processing executed by each processor core. Therefore, it is thought to be favorable to control power consumption for each processor core in a multi-core processor, instead of executing processor control described in Patent Document 1.
However, in a multi-core processor having a large-scale shared cache and the like, one operation acts on a plurality of components such as a register, an arithmetic unit, a cache memory and an external memory. Thus, in order to measure power consumption directly, a huge information collection network is necessary, and it may cost much. Therefore, it is difficult to measure power consumption including that of a portion shared by the respective processor cores. Moreover, even if such an information collection network is realized, it is very difficult to divide power consumption of a shared resource such as a shared cache to the respective cores, and it is difficult to measure power consumed by each core. Because of the abovementioned problems, there arises a problem that it is difficult to control power consumption of each processor core.
As stated above, there arises a problem that it is difficult to control power consumption of each processor core in a multi-core processor.